1. Field of the Invention
This invention relates to a semiconductor integrated circuit such as a memory, photoelectric converting device or signal processing device to be mounted on various electronic instruments, and particularly to its electrode structure.
2. Related Background Art
In recent years, there has been an interest in making a semiconductor circuit device highly integrated, for example to provide a practical application of a semiconductor functional element finely worked such as the development of an MOS transistor with a gate length of submicron order. More specifically, in the case of an MOS transistor with a gate length of 0.8 .mu.m, the area occupied by the element is about 20 .mu.m.sup.2, having a structure suitable for higher integration.
However, even if the semiconductor functional element may be made finer effecting higher integration, it has been difficult to obtain good characteristics as expected while maintaining high yield. This point has been considered in the prior art to be a problem concerning semiconductor functional element, formation, and necessarily importance has been placed on improvement in the process for formation of semiconductor functional element. That is, it has been strongly recognized that determining how to form the element capable of good actuation stably and with good reproducibility should be the way of improving the yield.
However, as the result of detailed studies of the element structure or element formation process by the present inventors, it has been found that the yield can be greatly improved, and the performance also improved, by constituting the electrode structure.
FIGS. 11A, 11B and 11C are schematic views for illustration of the structure of MOSFET of the prior art example as described above, which correspond respectively the perspective view, the top view and the sectional view.
In the n type semiconductor substrate 1, P type wells are formed, and n.sup.+ type source-drain regions 3, 4 are formed at intervals therein. On this semiconductor substrate, an insulation film 8 is formed, and at the portions corresponding to source-drain, contact holes CH are respectively formed by etching. Also, between the source and drain, a gate electrode 5 is arranged.
Within the contact hole CH and on a part of the insulation film 8, Al, which becomes the source-drain electrode and the source-drain electrode wiring is formed as shown by deposition patterning.
The structure of the Al electrode within the contact hole will now be described.
The contact hole CH has a rectangular opening with a shorter width w and a longer length 1 according to the design of the mask for etching, and its depth h corresponds to the thickness of the insulation film on the source-drain regions 3, 4.
In such constitution of the prior art, in view of the step coverage at the edge portion or the mask slippage, usual representative values are made 0.5 to 1.0 .mu.m for M, 0.5 to 1.0 .mu.m for N, 0.5 to 1.0 .mu.m for w of the opening, 0.5 to several .mu.m for 1 and 0.5 to 0.8 .mu.m for h.
However, in a semiconductor device having the electrode structure of the prior art as in the example as described above, even if the gate length can be made small to submicron order (0.1 .mu.m order) by finer formation, M could be made only as small as 1 .mu.m as the smallest. Because of the problems such as step coverage and mask slippage, when it is attempted to make M smaller than this, the yield of the semiconductor will become extremely poor.
Thus, according to the findings by the present inventors, it has been found that one of the factors which has remarkable effects for speedup of the finer semiconductor device or correspondence to large current driving for that purpose is the distance M between the above-mentioned control electrode and the main electrode, and this point should be improved and also other parasitic capacity and parasitic resistance should be reduced.
As a transistor in which only the point of M has been improved, there is a structure of SST (Super Selfalign Transistor) as shown in FIG. 12.
Here, a base electrode 1120 comprising a polysilicon doped with boron (B) and an emitter electrode comprising polysilicon doped with arsenic (As) are constituted proximate to each other. However, because the electrode is constituted of a polysilicon and the contact portion between the electrode and the base wiring 1122 must at a position apart from the base region 1114, there are technical tasks to be solved to avoid difficulty in providing an increase of base resistance and overall finer formation.
In this Figure, 1111 is a semiconductor substrate, 1112 an n.sup.+ collector embodding layer, 1113 an n.sup.- collector layer, 1114 a P base layer, 1115 a P.sup.+ base layer, 1116 an n.sup.+ emitter layer, 1117 an n.sup.+ collector layer, 1118 an n.sup.+ layer, 1119 a polysilicon collector electrode, 1120 a polysilicon base electrode, 1121 a polysilicon emitter electrode, 1122 an Al base wiring, 1123 an Al collector wiring, 1130 a field insulation film, and 1131, 1132, 1133 are insulation films.